Use of a context identifier in a cache memory

ABSTRACT

A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may be compared with the context identifier in the cache line&#39;s tag. The cache line&#39;s data block may be transferred if the context identifiers and the tags match.

FIELD OF THE INVENTION

[0001] This invention relates to computer technology. More particularly,this invention relates to improving the performance of cache memory in acomputing device.

BACKGROUND OF THE INVENTION

[0002] The use of one or more cache memory systems within a computer'smemory hierarchy is a well-known technique to increase the performanceof a computer (see e.g., Handy, Jim; The Cache Memory Book; AcademicPress, 1998). FIG. 1 illustrates a typical cache memory array 100. Cachememory array 100 includes cache lines 110. Each cache line includes atag 120 and a data block 130. Example cache line 140 includes tag 150and data block 160. Reference numeral 170 illustrates that example tag150 is a portion of main memory address 170. Main memory address 170 isthe main memory address corresponding to data block 160.

[0003] Processors transfer instructions and operands back and forthbetween the execution core of the processor and the computer's memoryhierarchy during memory transfers. Examples of memory transfers areloading instructions/operands from the memory hierarchy to the processorand storing instructions/operands from the processor to the memoryhierarchy. During a memory transfer, the processor generates a mainmemory address. A portion of the main memory address is compared withthe entries in tag 120 during a cache look-up to determine whether cachearray 100 contains an entry corresponding to the memory transfer. Asdemonstrated by the relationship between tag 150 and main memory address170, the process of a cache look-up is accelerated by requiring theprocessor to compare only a portion of each main memory address witheach entry in the tag. Typically, cache memory uses a portion of eachlinear address generated by the processor to index data stored in cachearray 100.

[0004] A thread is a part of a computer program that can executeindependently of other parts of the computer program. The performance ofa processor can be enhanced if multiple threads are executedconcurrently on the processor. Concurrent execution of multiple threadsis possible if the dependencies among the various instructions of themultiple threads are detected and properly managed.

[0005]FIG. 2 illustrates how many Intel® processors use a virtual memoryenvironment to allow a large linear address space to be supported by asmall amount of physical memory (e.g., random access memory). During amemory transfer, a processor generates a linear address 210. Linearaddress 210 comprises a directory field 220, a table field 225, and anoffset field 230. The base of the page directory 235 is contained incontrol register CR3 240. The directory entry 220 of linear address 210provides an offset to the value contained in control register CR3 240.The page directory contains a page table base pointer 245. Table field225 provides an offset that is combined with page table base pointer 245to identify the base of the page that contains the physical address 255.Offset field 230 is combined with the page table entry to identify thephysical address 255.

[0006]FIG. 3 illustrates a shortcoming associated with performing cachelook-ups with only a partial main memory address. A processor (notshown) generates linear addresses 304 and 306 in response to loadinstructions LD0 and LD1. 305 and 307 illustrate the portion of eachaddress that is used to perform a cache look-up. While 305 and 307appear to be identical, they are only a portion of 304 and 306respectively. 304 and 306 map to two different physical addressesbecause each address has a different entry in their respective directoryfields (320 and 325) and offset fields (330 and 335). An additionalcomplication is introduced when, as in FIG. 3, a processor supportsconcurrent execution of multiple threads. Thread 0 and Thread 1 can havedifferent values for the bases of their respective page directories (340and 345). Thus, even if 304 and 306 were the same, they would map to twodifferent physical addresses.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The invention is illustrated by way of example, and not by way oflimitation, in the figures of the accompanying drawings in which likereference numerals refer to similar elements.

[0008]FIG. 1 is a diagram of a prior art cache memory array.

[0009]FIG. 2 is a conceptual illustration of mapping a linear address toa physical address.

[0010]FIG. 3 is a conceptual illustration of two similar tags that mapto two different physical addresses.

[0011]FIG. 4A is a diagram of one embodiment of a cache memory arrayusing a context identifier.

[0012]FIG. 4B is a conceptual illustration of one embodiment of acontext identifier.

[0013]FIG. 5 is a simplified block diagram of one embodiment of acontext identifier generator and related control circuitry.

[0014]FIG. 6 is a block diagram of one embodiment of a cache memorysystem.

[0015]FIG. 7 is a block diagram of one embodiment of a cache memorysystem.

DETAILED DESCRIPTION

[0016] Use of a context identifier in cache memory is described herein.In the following description, numerous specific details are provided inorder to provide a thorough understanding of embodiments of theinvention. One skilled in the relevant art will recognize, however, thatthe invention can be practiced without one or more of the specificdetails, or with other methods, components, materials, etc. In otherinstances, well-known structures, materials, or operations are not shownor described in detail to avoid obscuring aspects of the invention.

[0017] Reference throughout this specification to “one embodiment” or“an embodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present invention. Thus, theappearances of the phrases “in one embodiment” or “in an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in any suitable manner inone or more embodiments.

[0018] Cache memory systems index cache lines with a portion of a linearaddress called a tag. A processor generates the linear address during amemory transfer operation. A portion of the linear address is comparedwith the tags during a cache look-up. Many Intel® processors provide amechanism to ensure that an apparent match between a partial address anda tag is a true match. This mechanism is called the hit/missdeterminator. The hit/miss determinator operates in parallel with thecache look-up process of cache memory. The hit/miss determinatorconverts a linear address associated with an issued instruction to thecorresponding physical address and compares that physical address withthe full address associated with the tag that matches the partial linearaddress. The hit/miss determinator is much slower than cache memorybecause it must translate linear addresses into physical addresses andbecause it performs comparisons of complete addresses. If the hit/missdeterminator detects that cache memory has produced a false match, itcorrects the mistakes made by cache memory. The process of detecting andresponding to errors introduced by a false match in cache memory candegrade processor performance.

[0019]FIG. 4A illustrates one embodiment of a cache memory arrayincorporating a context identifier. Cache memory array 400 includes anumber of cache lines 410. Each cache line 410 includes contextidentifier 405, tag 420, and data block 430. Thus, cache line 440Aincludes context identifier 415A and tag 450A. Similarly, cache line440B includes context identifier 415B and tag 450B. Two differentthreads generated context identifiers 415A and 415B.

[0020] Linear addresses 470A and 470B correspond to tags 450A and 450B.In FIGS. 4A and 4B, linear addresses contain context identifiers toillustrate how context identifiers can be used to distinguish betweensimilar linear addresses. Context identifiers are not part of a linearaddress, however, and are generated separately from the linearaddresses.

[0021] Cache memory systems implemented according to the prior artconduct cache look-ups by comparing a partial linear address generatedby a processor (not shown) with each tag 420 in cache array 400. If theprocessor generated a partial linear address of 123, then that addresswould match both tag 450A and tag 450B. As stated above, a hit/missdeterminator ultimately determines which cache line, if either, matchesthe main memory address generated by the processor. Prior art systemsincur a performance penalty when the hit/miss determinator manages andcorrects false matches between a partial linear address and a tag 420.

[0022]FIG. 4B illustrates the use of context identifiers to reduce thefrequency of a false match between a partial linear address generated bythe processor and a tag 420. Linear addresses 470A and 470B areassociated with cache lines 440A and 440B of FIG. 4A. Address 475 isgenerated by a processor in response to an issued instruction. Address475 includes context identifier 480 and partial linear address 485. Aprior art cache might have identified a false match between 475 and 470Bbecause partial linear address 485 matches tag 450B. In one embodiment,context identifier 480 is compared with context identifier 415B. Also,in one embodiment partial linear address 485 is compared with tag 450B.Thus, cache array 400 will not find a false match between 475 and 470Bbecause context identifier 480 does not match context identifier 415B.

[0023]FIG. 5 illustrates one embodiment of a portion of a page misshandler (PMH). In one embodiment, PMH 500 generates and controls theassignment of context identifiers. PMH 500 includes context identifiergenerator 510, comparator 520, context identifier multiplexer 530, andinverter 540. In one embodiment, context identifier generator 510generates a one bit binary number corresponding to a currently executingthread. In alternate embodiments of the invention, context identifiergenerator 510 generates a binary number with more than one bit.Comparator 520 compares the addresses of the bases of the pagedirectories used by two threads that are executing on a processor. In adifferent embodiment, the context identifier comprises two or more bits.

[0024] According to one embodiment, PMH 500 determines whether or notthe same context identifier is assigned to the instructions of twodifferent threads. For the embodiment shown in FIG. 5, PMH 500 assigns afirst context identifier to a first thread that executes on theprocessor. For example, if Thread 0 is the first thread to execute onthe processor, the processor may assign 0 as Thread 0's contextidentifier. The context identifier is not required to match the threadnumber. Thus, Thread 0 may have a context identifier of either 1 or 0.In alternate embodiments of the invention, a processor executes morethan two threads of instructions and context identifiers of more thanone bit are used.

[0025] If a second thread begins to execute on the processor (e.g.,Thread 1), PMH 500 determines whether to assign the instructions of thesecond thread a different context identifier than was assigned to theinstructions of Thread 0. It is possible that Thread 0 and Thread 1 areusing the same pages in main memory. If so, then it is desirable toassign the same context identifier to the instructions of the twothreads because a false match between a tag and a linear address is lesslikely when the linear address is known to map to the same page as thetag. Comparator 520 determines whether Thread 0 and Thread 1 are usingthe same pages in main memory by comparing the bases of the pagedirectories used by the two threads.

[0026] If Thread 0 and Thread 1 are using the same address as the basefor their respective page directories, multiplexer 530 will select thesame context identifier for Thread 1 as it selected for Thread 0.Conversely, if comparator 520 indicates that Thread 0 and Thread 1 arenot using the same address for the bases of their page directories,multiplexer 530 selects the output of inverter 540 as the contextidentifier for Thread 1. Determining whether two threads share the samecontext identifier can be implemented in a different manner. Forexample, in an embodiment of the invention, the operating systemdetermines whether two threads share the same context identifier andexplicitly tells the processor the correct context identifier toassociate with a thread. In yet another embodiment of the invention, apredictor that studies the memory access patterns of the threadspredicts the context identifier. According to one embodiment, a user mayinstruct PHM 500 to always select the same value for the instructions oftwo different threads or to always select a different context identifiervalue for the instructions of two different threads. Also, someembodiments make use of additional criteria besides the address of thebase directory, to determine whether two threads share the same contextidentifier.

[0027] In alternate embodiment of the invention, more than two threadsare present in the processor. For an embodiment where n threads arepresent in the processor, the context identifiers are extended to anencoding scheme that allows for n different context identifiers to bespecified. A person of ordinary skill in the art will see that when an nbit context identifier is used, the n bits are placed in the cache inthe same way that a single bit is placed in the cache. Also, a person ofordinary skill in the art will see that comparing n bit contextidentifiers to each other can be done in nearly the same way ascomparing two single bit context identifiers.

[0028] An embodiment of the invention with multiple threads uses a poolof unused context identifiers. When a thread changes its page table base(CR3), it compares the new value to the value of the page table baseused by other active threads or any valid page table base of a contextidentifier in the pool. If there is a match, it takes the value of thecontext identifier of the thread that produced the match. If there isnot a match with another active thread, it takes an unused contextidentifier from the pool. Context identifiers are returned to the unusedpool when either a thread changes its page base value, or the last lineof cache with a given context identifier is deallocated. The latterarrangement allows a thread to hit on data that a previous threadbrought in. A person of ordinary skill in the art will see that manyschemes for predicting the value of a context identifier for a threadcan be used.

[0029]FIG. 6 illustrates a read from a cache memory system having acontext identifier. Cache array 610 includes cache lines 605. Each cacheline 605 includes a context identifier 610A, a tag 610B, and a datablock 610C. Cache array 610 is coupled to cache controller 620. Cachecontroller 620 controls access to the data contained in cache array 610.

[0030] Cache controller 620 is coupled to hit/miss determinator 670 andcomparators 675 and 680. The operation of hit/miss determinator 670 andcomparators 675 and 680 is discussed below. In one embodiment,comparator 675 is coupled to AGU 630 as well as AND gate 685. AGU 630generates linear addresses for issued instructions that require a memorytransfer (e.g., LOAD and STORE instructions). In one embodiment,comparator 680 is coupled to AND gate 685 and PMH 640 throughmultiplexer 650. PMH 640 contains control logic used to determine whichcontext identifier is assigned to which issued instruction.

[0031] A read cycle is typically initiated by an issued LOAD instruction(LD) 660. LD 660 is sent to PMH 640 and AGU 630. PMH 640 determines,among other things, which thread is the source of LD 660. PMH 640assigns a context identifier to LD 660 based, in part, on which threadis the source of LD 660. PMH 640 issues a context identifier associatedwith LD 660 to comparator 680 through multiplexer 650. Similarly, AGU630 issues a partial linear address to comparator 675.

[0032] Comparators 675 and 680 use the partial linear address and LD660's context identifier to determine whether cache array 610 containsthe information that LD 660 requires. If cache array 610 contains therequired information a cache hit results. If cache array 610 does notcontain the required information a cache miss results.

[0033] A cache hit requires that a particular cache line contain acontext identifier that matches LD 660's context identifier and a tagthat matches the partial linear address corresponding to LD 660.Comparators 675 and 680 compare the tag field and the context identifierfield of each cache line with LD 660's context identifier and partiallinear address. According to one embodiment, there are as manycomparators as there are cache lines so that comparisons can be done ina single parallel operation. If a single cache line contains a contextidentifier and a tag that matches LD 660's context identifier andpartial linear address, then AND gate 685 signals a cache hit. Thepossibility exists, however, that the cache hit is based on a falsematch because comparator 675 compares only a portion of LD 660's addresswith each tag in cache array 610A.

[0034] Hit/miss determinator 670 detects whether a cache hit is based ona false match. Hit/miss determinator receives the full linear address ofthe location in main memory from which LD 660 requires aninstruction/operand. According to one embodiment, hit/miss determinator670 translates the linear address conveyed to it by the AGU to aphysical address. Hit/miss determinator 670 determines the physicaladdress corresponding to the tag matching LD 660's partial linearaddress. Hit/miss determinator 670 compares both complete physicaladdresses to determine whether the cache hit is based on a false match.

[0035]FIG. 7 illustrates a write to cache memory using a contextidentifier. Cache array 710 includes a number of cache lines 705. Eachcache line 705 includes a context identifier 710A, a tag 710B, and adata block 710C. Cache array 710 is coupled to cache controller 720.Cache controller 720 performs a number of functions includingdetermining into which cache line a block of data will be written. Cachecontroller 720 is coupled to AGU 730 and PMH 740 through mulitplexer750.

[0036] Issued instruction 760 is sent from the processor (not shown) toPMH 740 and AGU 730. In one embodiment, AGU 730 generates a linearaddress when issued instruction 760 requires a memory transfer. AGU 730is generally part of the processor's execution core. In otherembodiments AGU 730 may generate a physical address. In one embodiment,PMH 740 generates at least two context identifiers and the controlsignals that control multiplexer 750. In other embodiments, PMH 740 maygenerate any number of context identifiers.

[0037] A write cycle is typically initiated by an issued storeinstruction (ST) (e.g., ST 760). ST 760 is sent to PMH 740 and AGU 730.PMH 740 determines which thread is the source of ST 760. PMH 740 furtherdetermines which context identifier to assign to ST 760. According toone embodiment, PMH 740 has three modes of operation: OFF, NON-SHARED,and ADAPTIVE. If PMH 740 is operating in the OFF mode, then PHM 740 maywrite the same value for each context identifier. A cache line is sharedby the instructions of two or more threads if the threads have the samecontext identifier as the context identifier stored in the cache line.

[0038] When operating in the NON-SHARED mode, PMH 740 may assign acontext identifier that is particular to the thread that contains theissued instruction. In one embodiment, the ADAPTIVE mode allows PMH 740to dynamically determine whether to assign the same or different contextidentifiers for instructions originating from different threads. In oneembodiment, if the threads share the same address for the base of theirpage directories, then PMH 740 dynamically assigns the same contextidentifier for the instructions contained in the threads. If not, in anembodiment, then PMH 740 dynamically assigns different contextidentifiers to the instructions contained in the threads.

[0039] In one embodiment, PMH 740 considers whether the computer is inmulti-threaded mode and whether paging is enabled when determiningwhether to write the same context identifier for the instructions of twodifferent threads. Any number of criteria may be used to determine thevalue of a context identifier that is assigned to an issued instruction.Further, the context identifier generator and related control logic canbe located in a number of places within an electronic system and neednot be contained in the PMH or similar unit.

[0040] PMH 740 sends a context identifier appropriate for ST 760 tocache controller 720, through multiplexer 750. AGU 730 generates alinear address corresponding to the main memory location to which ST760A seeks to store data. AGU 730 provides cache controller 720 andhit/miss determinator 770 with the linear address corresponding to ST760. Cache controller 720 applies a cache line replacement policy todetermine which cache line will be used to store data for ST 760. Cacheline replacement policies are well known in the art (see e.g., Handy,Jim; The Cache Memory Book; Academic Press, 1998 for a more detaileddescription of cache line replacement policies).

[0041] After selecting an appropriate cache line, cache controller 720writes the context identifier to the context identifier field 780A ofthe selected cache line 780. Cache controller 720 writes a portion of ST760's linear address to the tag field 780B of cache line 780. In oneembodiment, the tag comprises bits 23 to 12 of a 32 bit linear address.There are many combinations of address bits that may be used for thetag. The cache controller writes the data associated with ST 760 intodata block field 780C of selected cache line 780. Cache management canbe controlled by instructions from an electronically accessible medium,which may be used to program a computer (or other electronic devices) toperform a process described herein. The electronically accessible mediummay include, but is not limited to, floppy diskettes, optical disks,CD-ROMs, magneto-optical disks, ROMs, RAMs, EPROMs, EEPRPOMs, magnet oroptical cards, flash memory, or other type of media/machine-readablemedium suitable for storing electronic instructions. Moreover, theinstructions may also be downloaded as a computer program product,wherein the program may be transferred from a remote computer to arequesting computer by way of data signals embodied in a carrier wave orother propagation medium via a communications link (e.g., a modem or anetwork connection).

[0042] The above description of illustrated embodiments of the inventionis not intended to be exhaustive or to limit the invention to theprecise forms disclosed. While specific embodiments of, and examplesfor, the invention are described herein for illustrative purposes,various equivalent modifications are possible within the scope of theinvention, as those skilled in the relevant art will recognize.

[0043] These modifications can be made to the invention in light of theabove detailed description. The terms used in the following claimsshould not be construed to limit the invention to the specificembodiments disclosed in the specification and the claims. Rather, thescope of the invention is to be determined entirely by the followingclaims, which are to be construed in accordance with establisheddoctrines of claim interpretation.

What is claimed is:
 1. A method comprising: storing a context identifierassociated with a tag in a cache memory; generating an address that isassociated with an issued instruction; comparing an address portion withthe tag, to determine if the address matches the tag; and comparing acontext identifier associated with the issued instruction with thecontext identifier stored in the cache memory, to determine if thecontext identifier associated with the issued instruction matches thecontext identifier stored in the cache.
 2. The method of claim 1 furthercomprising: transmitting a data block from the cache memory to aprocessor if the address portion matches the tag and if the contextidentifier associated with the issued instruction matches the contextidentifier stored in the cache memory.
 3. The method of claim 1 furthercomprising: replacing a data block of a cache line in the cache memorythat is selected by a replacement policy with a data block as specifiedby the address if the address portion does not match the tag; andstoring the context identifier in the cache line.
 4. The method of claim1 further comprising: replacing a data block of a cache line in cachememory that is selected by a replacement policy with a data block asspecified by the address if the address portion does match the tag andthe context identifier associated with the instruction does not matchthe context identifier stored with the tag; and storing the contextidentifier in the cache line.
 5. A method comprising: comparing anaddress of a base of a page directory used by a first thread with anaddress of a base of a page directory used by a second thread, todetermine if the address of the base of the page directory used by thefirst thread matches the address of the base of the page directory usedby the second thread; assigning a context identifier to both the firstthread and the second thread if the address of the base of the pagedirectory used by the first thread matches the address of the base ofthe page directory used by the second thread; and assigning a differentcontext identifier to the first thread and the second thread if theaddress of the base of the page directory used by the first thread doesnot match the address of the base of the page directory used by thesecond thread.
 6. The method of claim 5 further comprising: storing theaddress of the base of the page directory of the first thread in a firstregister; storing the address of the base of the page directory of thesecond thread in a second register; reading the first register todetermine the address of the base of a page directory of the firstthread; and reading the second register to determine the address of thebase of the page directory of the second thread.
 7. The method of claim6 wherein the first register and the second register are the sameregister.
 8. The method of claim 5 wherein the same context identifieris assigned to the first thread and the second thread.
 9. The method ofclaim 5 wherein a different context identifier is assigned to the firstthread and the second thread.
 10. An apparatus comprising: a contextidentifier generator for generating context identifiers; a control unitcoupled to the context identifier generator to assign contextidentifiers to cache lines; and a cache coupled to the control unithaving a plurality of cache slots to store a plurality of cache lines,each of the cache lines including at least a context identifier, a tag,and a data block.
 11. The apparatus of claim 10 wherein the control unitfurther comprises: one or more registers to store the addresses of oneor more bases of one or more page directories; and a comparator coupledto the register to compare the address of a base of a page directoryused by a first thread with the address of a base of a page directoryused by a second thread.
 12. The apparatus of claim 10 furthercomprising a multiplexer coupled to the comparator and with the contextidentifier generator to select context identifiers.
 13. The apparatus ofclaim 12 wherein each context identifier comprises one or more bitscorresponding to a page directory base pointer that is a physicaladdress of a base of a page directory.
 14. The apparatus of claim 13wherein the context identifier comprises one or more bits of the tag.15. An apparatus comprising: an address generating unit (AGU) togenerate addresses in response to an instruction issued by a processor;a cache to store a plurality of cache lines, each of the plurality ofcache lines including at least a context identifier, a tag, and a datablock; at least one comparator coupled to the AGU and coupled to thecache to compare an address portion generated by the AGU with each ofthe tags in each of the plurality of cache lines; a control unit togenerate two or more context identifiers and to select one of the two ormore context identifiers; and at least one comparator coupled to thecontrol unit and coupled to the cache to compare the context identifierselected by the control unit with each of the context identifiers ineach of the plurality of the cache lines.
 16. The control unit of claim15 further comprising: a first register to store an address of a base ofa page directory associated with a first thread of executing computerinstructions; a second register to store an address of a base of a pagedirectory associated with a second thread of executing computerinstructions; a comparator coupled to the first register and the secondregister to compare the value stored in the first register with thevalue stored in the second register; a context identifier generator togenerate at least two context identifiers; and a multiplexer coupled tothe context identifier generator and the comparator to select one of theat least two context identifiers.
 17. The control unit of claim 16wherein: the multiplexer is to select a first context identifier if theaddress of the base of the page directory associated with the firstthread of executing computer instructions matches the address of thebase of the page directory associated with the second thread ofexecuting computer instructions; and the multiplexer is to select asecond context identifier if the address of the base of the pagedirectory associated with the first thread of executing computerinstructions does not match the address of the base of the pagedirectory associated with the second thread of executing computerinstructions.
 18. An article comprising a machine readable mediumstoring information representing a processor, the processor comprising:a context identifier generator for generating context identifiers; acontrol unit coupled to the context identifier generator to assigncontext identifiers to cache lines; and a cache coupled to the controlunit having a plurality of cache slots to store a plurality of cachelines, each of the cache lines including at least a context identifier,a tag, and a data block.
 19. The article of claim 18 further comprising:one or more registers to store the addresses of one or more bases of oneor more page directories; and a comparator coupled to the register tocompare the address of a base of a page directory used by a first threadwith the address of a base of a page directory used by a second thread20. The article of claim 19 further comprising a multiplexer coupled tothe comparator and with the context identifier generator to selectcontext identifiers.
 21. An article comprising a machine readable mediumstoring information representing a processor, the processor comprising:a cache memory to store a plurality of cache lines, each cache linehaving an associated tag and an associated context identifier; andcomparison logic to compare a request tag and a request contextidentifier to said associated tag and said associated context identifierfor each one of said plurality of cache lines.
 22. The articlecomprising a machine readable medium storing information representing aprocessor of claim 21, wherein said associated context identifiercomprises a thread identifier.
 23. The article comprising a machinereadable medium storing information representing a processor of claim 21wherein in a first mode, said associated context identifier comprises athread identifier, and wherein in a second mode, said associated contextidentifier is a predicted context identifier.
 24. The article comprisinga machine readable medium storing information representing a processorof claim 23 wherein in said second mode, said predicted contextidentifier is determined, at least in part, by comparing a base of apage directory used by a first thread with a base of a page directoryused by a second thread, to determine if the base of the page directoryused by the first thread matches the base of the page directory used bythe second thread.
 25. The article comprising a machine readable mediumstoring information representing a processor of claim 21, wherein saidcomparison logic is to generate a hit signal only if a contextidentifier match and a tag match occurs.
 26. An apparatus comprising: acache memory to store a plurality of cache lines, each cache line havingan associated tag and an associated context identifier; and comparisonlogic to compare a request tag and a request context identifier to saidassociated tag and said associated context identifier for each of saidplurality of cache lines.
 27. The apparatus of claim 26 wherein saidassociated context identifier comprises a thread identifier.
 28. Theapparatus of claim 26 wherein in a first mode, said associated contextidentifier comprises a thread identifier, and wherein in a second mode,said associated context identifier is a predicted context identifier.29. The apparatus of claim 28 wherein in said second mode, saidpredicted context identifier is determined, at least in part, bycomparing a base of a page directory used by a first thread with a baseof a page directory used by a second thread, to determine if the base ofthe page directory used by the first thread matches the base of the pagedirectory used by the second thread.
 30. The apparatus of claim 29wherein in said second mode, said predicted context identifier isdetermined, at least in part, by comparing a base of a page directoryused by a first thread with a base of a page directory used by a secondthread and a base of a page directory used by a third thread, todetermine if the base of the page directory used by the first threadmatches the base of the page directory used by either the second or thethird threads.
 31. The apparatus of claim 26 wherein said comparisonlogic is to generate a hit signal only if a context identifier match anda tag match occurs.